1. Field of the Invention
The present invention relates to a solid-state imaging device including a plurality of vertical charge transfer portions and a horizontal charge transfer portion that is connected to one end or both ends of the vertical charge transfer portions.
2. Description of Related Art
An interline transfer solid-state imaging device includes a plurality of photoelectric conversion portions that are arranged in a matrix, plural rows of vertical charge transfer portions that are arranged in correspondence with respective rows of the photoelectric conversion portions, a horizontal charge transfer portion that is connected electrically to one end of each of the vertical charge transfer portions and an output circuit portion that is connected to one end of the horizontal charge transfer portion. In such a solid-state imaging device, signal charges generated in the photoelectric conversion portions are transferred vertically by the vertical charge transfer portions to the horizontal charge transfer portion, transferred horizontally (in a direction perpendicular to the transfer direction in the vertical charge transfer portions) by this horizontal charge transfer portion, and then reach the output circuit portion.
FIGS. 21 to 23 are schematic views showing a structure in the vicinity of a connection portion of a vertical charge transfer portion and a horizontal charge transfer portion in a conventional interline transfer solid-state imaging device, with FIG. 21 being a plan view, FIG. 22 being a sectional view taken along line A-A′ in FIG. 21, and FIG. 23 being a sectional view taken along line B-B′ in FIG. 21. In these figures, numeral 401 denotes a vertical charge transfer portion, numeral 416 denotes a connection portion of the vertical charge transfer portion and a horizontal charge transfer portion, numeral 403 denotes the horizontal charge transfer portion, numeral 405 denotes an N-−−-type semiconductor substrate, numeral 406 denotes a P-type well layer, numeral 407 denotes a P+-type element isolation region, numeral 408 denotes an N-type semiconductor region, numerals 409a, 409b and 409c denote N−-type semiconductor regions, numeral 410 denotes an insulating film, numerals 411, 412a, 412b and 413 denote vertical transfer electrodes, numerals 414a and 414b denote first horizontal transfer electrodes, and numerals 415a and 415b denote second horizontal transfer electrodes.
The vertical charge transfer portion 401 includes the N−−-type semiconductor substrate 405, the P-type well layer 406 formed on the surface of the N−−type semiconductor substrate 405, and the N-type semiconductor region 408 serving as a vertical transfer channel region formed on the surface of the P-type well layer 406. On this N-type semiconductor region 408, a plurality of the vertical transfer electrodes 411, 412a, 412b and 413 are formed via the insulating film 410. Each of the vertical transfer electrodes is wired so as to be supplied with a clock pulse φV1, φV2, φV3 or φV4.
In the horizontal charge transfer portion 403, the N-type semiconductor region 408 serving as a horizontal transfer channel region is formed on the surface of the above-mentioned P-type well layer 406. On this N-type semiconductor region 408, a plurality of the first horizontal transfer electrodes 414a and 414b are formed via the insulating film 410. Further, a space between the first horizontal transfer electrodes is provided with the N-type semiconductor region 409a, on which the second horizontal transfer electrodes 415a and 415b are formed via the insulating film 410. Each of the horizontal transfer electrodes is wired so as to be supplied with a clock pulse φH1 or φH2.
Also, in the connection portion 416 of the vertical charge transfer portion and the horizontal charge transfer portion, the vertical transfer electrode 413 that is arranged at the terminating end of the vertical charge transfer portion 401 (in the following, referred to as “the final vertical transfer electrode”) and the first horizontal transfer electrode 414a are arranged so as to have a space therebetween, where the N-type semiconductor region 409b is formed. In addition, the second horizontal transfer electrode 415a covers this N-type semiconductor region 409b. 
Next, a charge transfer operation from the vertical charge transfer portion to the horizontal charge transfer portion in the above-described solid-state imaging device will be explained referring to FIGS. 24 to 26. FIG. 26 illustrates an example of a dock pulse to be applied to each of the transfer electrodes in the vertical charge transfer portion and the horizontal charge transfer portion. FIGS. 24 and 25 show a potential distribution during charge transfer from the vertical charge transfer portion to the horizontal charge transfer portion when being driven by the dock pulse shown in FIG. 26, with FIG. 24 showing the potential in the vicinity of the connection portion of the vertical charge transfer portion and the horizontal charge transfer portion and FIG. 25 showing that in the horizontal charge transfer portion. In these figures, a downward arrow indicates a positive direction of the potential, and the charge is stored in a diagonally shaded area (the same will apply to the following description).
At time t1, a signal charge 417 in the vertical charge transfer portion 401 is accumulated below the vertical transfer electrodes 411 and 412b that are supplied with a high voltage VVH. Then, at time t2, the pulse φV4 changes from VHL to VHH and the pulse φV2 changes from VHH to VHL, whereby a part of the signal charge 417 begins to be transferred from the vertical charge transfer portion 401 to the horizontal charge transfer portion 403. Next, at time t3, the pulse φV1 changes from VHL to VHH and the pulse φV3 changes from VHH to VHL, whereby the signal charge 417 further is transferred from the vertical charge transfer portion 401 to the horizontal charge transfer portion 403. At time t4, the pulse φV2 changes from VHL to VHH and the pulse φV4 changes from VHH to VHL, whereby the transfer operation of the signal charge 417 from the vertical charge transfer portion 401 to the horizontal charge transfer portion 403 ends. At this time, the signal charge 417 is accumulated below the first horizontal transfer electrode 414a that is supplied with VHH in the horizontal charge transfer portion 403. The next signal charge 418 already is transferred to the portion below the vertical transfer electrodes 411 and 412a that are supplied with the high voltage VHH. At time t5, the pulse φV3 changes from VHL to VHH and the pulse φV1 changes from VHH to VHL, whereby the next signal charge 418 is transferred to the portion below the vertical transfer electrodes 411 and 412b that are supplied with the high voltage VV-H.
Thereafter, the horizontal charge transfer portion is activated, and at time t6, φH1 changes from VHH to VHL and φH2 changes from VHL to VHH, whereby the signal charge 417 that has been stored below the first horizontal transfer electrode 414a is now stored below the first horizontal transfer electrode 414b. Furthermore, at time t7, φH1 changes from VHL to VHH and φH2 changes from VHH to VHL, whereby the signal charge 417 that has been stored below the first horizontal transfer electrode 414b is now stored below the first horizontal transfer electrode 414a that is arranged further forward. By repeating this operation, the signal charges are transferred through the horizontal charge transfer portion.
As shown in FIG. 25, during the operation of the above-described solid-state imaging device, a potential barrier 419 is formed below the N−-type semiconductor region 409a in the horizontal charge transfer-portion. This potential barrier 419 suppresses a backward transfer of the charges in the horizontal charge transfer portion. Further, as shown in FIG. 24, a potential barrier 420 is formed below the N−-type semiconductor region 409b in the connection portion 416 of the vertical charge transfer portion and the horizontal charge transfer portion. This potential barrier 420 suppresses a backward transfer of the charges from the horizontal charge transfer portion to the vertical charge transfer portion.
However, as pixels become finer and the horizontal charge transfer portion is driven at a lower voltage in the conventional solid-state imaging device as described above, it becomes more difficult to transfer charges smoothly from the vertical charge transfer portion to the horizontal charge transfer portion. This leads to problems of a vertical line display abnormality, so-called black line defect, and a considerable drop of the transfer efficiency. Referring to FIGS. 21, 24 and 25, the cause of such problems will be explained in the following.
In the conventional solid-state imaging device, since finer pixels accompany a narrower repetition pitch of the horizontal charge transfer portion 403, it has been necessary to narrow the distance (LHBA) between the first horizontal transfer electrode 414a and the first horizontal transfer electrode 415a. On the other hand, the distance (LV-H) between the final vertical transfer electrode 413 and the first horizontal transfer electrode 414a of the horizontal charge transfer portion 403 can be designed irrespective of the finer pixels. Accordingly, as shown in FIG. 21, the conventional solid-state imaging device has been designed so that, as the pixels become finer, the distance (LV-H) between the final vertical transfer electrode 413 and the first horizontal transfer electrode 414a in the connection portion 416 is longer than the distance (LHBA) between the first horizontal transfer electrodes in the horizontal charge transfer portion. As a result, a short channel effect in the N−-type semiconductor region 409a in the horizontal charge transfer portion is larger than that in the N−-type semiconductor region 409b in the connection portion. Accordingly, as shown in FIGS. 24 and 25, the potential barrier 420 in the connection portion of the vertical charge transfer portion and the horizontal charge transfer portion is larger than the potential barrier 419 in the horizontal charge transfer portion. Therefore, even when the high voltage of the clock pulses φH1 and φH2 to be applied to the horizontal charge transfer portion 403 is set so that no transfer defect is generated in the horizontal charge transfer portion 403, a transfer hindrance 421 causes a transfer residue 422 of the signal charge in the charge transfer from the vertical charge transfer portion 401 to the horizontal charge transfer portion 403 at time t2 and time t3. This sometimes has caused a vertical line display abnormality, so-called black line defect. In other words, as the voltage of the clock pulses φH1 and φH2 to be applied to the horizontal charge transfer portion 403 is lowered, the transfer defect occurs in the connection portion of the vertical charge transfer portion and the horizontal charge transfer portion earlier than in the horizontal charge transfer portion 403 itself. Thus, it has been difficult to drive the horizontal charge transfer portion 403 at a lower voltage.